The Milan-X CPUs and V-Cache equipped Zen 3 CPUs that AMD has been talking up since earlier this year are headed to market in both servers and the wider consumer space. AMD confirmed today that it would ship its Milan-X CPUs with up to 64MB of additional L3 cache per chiplet in Q1 2022. There are up to eight chiplets in a single Milan-X Epyc CPU, which means these new CPUs offer up to 512MB of additional L3 cache.
Milan-X would be impressive for its stonkin’ huge L3 alone, but the fact that the cache is mounted vertically makes the project more interesting. This kind of 3D chip stacking has been discussed around the metaphorical campfire for many years, but we’ve never seen a server chip commercialized with slices of cache mounted on top of the die.
According to AMD’s previous disclosures, the L3 doesn’t occupy space above any of Ryzen / Epyc’s hot spots, and cooling the additional L3 array isn’t a problem. It’s not clear which server customers will be interested in this kind of capability, but adding an additional 64MB of cache per chiplet could leave certain server SKUs with a lot of L3 per die. A 16-core Epyc CPU with eight chiplets would offer 48MB of L3 per core, for example. There aren’t many workloads that benefit from such lopsided configurations, but AMD did claim a 66 percent performance improvement when comparing a 16-core Milan against a 16-core Milan X in an RTL verification workload.
One new tidbit AMD revealed is that it is explicitly committing to keeping Milan-X socket compatible with Milan and existing SP3 deployments. This implies (but does not prove) that Milan and Milan-X will support the same TDP brackets.
AMD has stated that its L3 is built on a density-optimized version of TSMC’s N7 process, which should make it reasonably power efficient. There’s still going to be a power hit associated with turning all that cache on, and we don’t know if there are any other improvements in Milan-X to compensate. Our guess is that the new Milan-X chips will clock at least a little lower than standard Milan, to compensate for the power requirements of the new cache. Alternately, it’s possible that AMD has found enough low-level improvements to the core (or to TSMC’s 7nm node) to keep clocks largely the same while adding the additional L3. AMD is keeping clocks and exact SKU details under wraps for now.
The fact that AMD still expects to ramp Genoa in 2022 indicates that Milan-X is more of a swan song for the existing SP3 ecosystem than a massive new project. The V-Cache enabled Zen 3 CPUs that are expected to launch for Socket AM4 in Q1 may be similarly positioned.
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